System for expanded detection and correction of errors in parallel binary data produced by data tracks

ABSTRACT

Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

O United States Patent 1151 3,675,200

Bossen et al. 1 July 4, 1972 541 SYSTEM FOR EXPANDED DETECTION 3,551,88612/1970 Cook ..340 14o.1 F AND CORRECTION OF ERRORS [N 3,5l8,625 6/1970Agin ..340/l46.l F LL N R DATA PRODUCED 3,142,829 7/1964 Comstock..340/l74.l B BY DATA TRACKS Primary ExaminerCharles E. Atkinson [72]Inventors: Douglas C. Bossen, Wappingers F ll Artorney-Hanifin andJancin and Julius B. Kraft Robert A. Henle, Hyde Park; Mu Y. l-lsiao,Poughkeepsie; Gerald A. Maley, Fishkill; 57 ABSTRACT W. 'd P N YPoughkeepsle of Errors in parallel binary data produced by a pluralityof data v track, e.g., a plurality of parallel shift registers, arecorrected I l Asfilgncci lfllel'naliollal Business Machines P by asystem in which the shift registers which are stuck, i.e., in-

' alterable, are determined and counted. By single Hamming [22] Fired;Nov. 23 1970 error detection means, the presence of a Hamming error andan indication of the bit position of a single Hamming error is PP 911726made. Comparison means determine if the indicated Hamming error iscoincident with a stuck track. Then, depen- [52] C| F, 340/1461 AL340/1741 B dent on the parity condition of the data as well as the countof 511 1111.01. ..G06f 11/08, 006k 5 00 Stuck tracks, apparatus isProvided for complementing one or [58] Field of Search ..340/l46.1 F,174.1 B; 235/153 more of the Stuck tracks and/or correcting theindicated Hamming error. [56] References Cited UNITED STATES PATENTS 38Claims, 9 Drawing Figures 3,262,097 7/1969 Miller ..340/l46.l F

48 86 C 84 1 LRACK w es 3 xo-lornzzzoo E zc-rcrnzxoo E VALVE=2\ 62\'VALVE=1 DECODER HAMMING ERROR DETECTOR 1 PASS I LATCH RESET DELAYPatented July 4, 1972 3,675,200

5 Sheets-Sheet 1 FIG.1

EVEN PARITY CORRECT & ERROR CONDITION EVEN PARITY CORRECT & ERRORCONDITION SAME FLOW CHART BRANCH AS FIG I FIG.6

I HALT I COMPALLELMENT m INVENTORS SIIII c K INI IcK STUCK TRACKSDOUGLAS CEBOSSEN Nor Pomm) To I ROBERT A. HENLE MU Y. HSIAO GERALD A.MALEY W. DAVID PRICER SET FIRST PASS INDICATOR By ATTORNEY Patented July4, 1972 3,675,200

5 Sheets-Sheet 2 SHIFT PULSE GENERATOR 1 COUNTER 13 mm 1 READ I -14 FIG.15? 0 2/-\ 2 0 3 0 DELAY -16 F 1 WRHE -15 F|G.2

11 st 2nd 7th p 1 L TRACK TRACK fL 10 10 10M GENERATOR 2 0 SHIFT PULSECHECK o o 1 1 11 11 1i19 i 17 RESET AA-18 A A A -18 TOT STUCK TRACKPatented July 4, 1972 5 Sheets-Sheet 5 TRACK m 5th FIG. 5

SYSTEM FOR EXPANDED DETECTION AND CORRECTION OF ERRORS IN PARALLELBINARY DATA PRODUCED BY DATA TRACKS BACKGROUND OF THE INVENTION 1. Fieldof the Invention The present invention relates to error correction of aparallel binary bit data pattern such as that constituting a word. Moreparticularly, it relates to a system which expands the potential oferror correcting and detecting codes, e.g., Hamming codes.

2. Description of the Prior Art The errors which occur in binary datapatterns utilized in digital computers may be conveniently put into oneof two catagories: transient or random errors and hard errors. Transienterrors may be due to an error in coding or in operating the computer orto stray or intermittent electronic effects in the computer circuitry.Transient errors are usually not repeated during subsequent similar dataprocessing operations. On the other hand, hard errors are due to somespecific malfunction in the computer circuitry and may be expected tocontinue to appear during subsequent operation.

Because of the high cost of computer time," it is, of course, desirableto maintain the computer in operating condition for as long as possible.Consequently, the art has devised self-correcting error codes for thecomputer which permit the computer to detect an error and correct theerror while continuing to routinely operate. It should be noted thatsuch error-correction techniques do not correct the cause of the error,but rather correct the data containing the indicated error. If the erroris a transient error, the cause of the error should quickly disappearand correct data will be produced during subsequent operation. However,even if the error is a hard error, the correction system couldcontinually correct such an error condition, thereby permitting thecomputer to continue to function and produce good data despite apermanent defect. This permits the computer to provide a maximum ofdesirable operative time.

The standard error-detecting and correcting codes presently being usedthroughout the art are Hamming codes. Such codes are described generallyin the text Introduction to Digital computers," Maley and Heilweil,Prentice Hall Inc, 1968, pp. 2830 and in the text Logical Design ofDigigal Computers," M. Phister, John Wiley & Sons, lnc., 1958, pp.329-330, and described in greater detail in the article Error Detectingand Error Correcting Codes," by R. W. Hamming, The Bell System TechnicalJournal, April 1950, pp. 147-160 and in U.S. Pat No. Re. 23,601, R. W.Hamming et al.

The most commonly used Hamming detecting and correcting code is asingle-error correcting code which can be used in combination with aparity check for the particular binary data pattern to provide asingleerror correcting double-error detecting code. In other words, withthis technique, a single detected error can be corrected. However, ifthere are two errors in the line of parallel binary data, this conditioncan be detected using the parity bit combination with the Hamming codemeans. This Hamming code cannot correct the double error condition.Further, three or more errors are not capable of detection. Whiledouble-error correcting and detecting code means have been disclosed inthe art, the system required to implement such double-error correctionis quite complex and relatively difficult to implement.

While the standard single-error correcting Hamming code means have beenfound to be entirely adequate for data stored in random access memorysystems, it is believed that singleerror correcting code means maypresent potential problems in correcting data taken from sequentialaccess storage devices, such as discs and drums and particularlyelectronically rotatable or cycling memory units. In such sequentialaccess storage devices, the binary data is stored in an array of banks,each of which contains a plurality of parallel rotating or cycling datatracks from which the parallel binary data or words are produced. Insuch sequential access storage means,

there appears to be an increased potential for errors in parallel dataremoved from the memory. This appears due to the likelihood that anerror at any point in a data track of a sequential access storage systemis likely to affect the whole track. On the other hand, in random accessmemory systems, it is less likely that an error in a particular cell orcore in a storage matrix will affect other units in the matrix. Thisgreater tendency towards errors in sequential access storage system isexpected to be particularly significant in sequential accesssemiconductor integrated circuit memory systems such as systemsemploying a plurality of shift register tracks formed on one or moresemiconductor chips.

A memory system of this type is described in copending ap plication Ser.No. 889,435, William Beausoleil, filed on Dec. 31, 1969 and now U.S.Pat. No. 3,648,255 issued Mar. 14, 1972. In this system, parallel binarydata is stored across a bank of electronically cycled tracks formed byintegrated circuit semiconductor elements. The tracks are shiftregisters; the data stored in these shift registers must be regeneratedperiodically. This is done by means of a high-speed clock operating inconjunction with a low-speed clock. During the inactive or storage cycleof the memory, the data stored in these shift register tracks isregenerated by slow cycling under control of the low-speed clock whichperiodically shifts each of the bits stored in the track to the nextsucceeding position. Then, during the active phase, when it is desiredto remove a word of data from across a bank of cycling shift registersor tracks, the data in the registers is cycled by shifting from oneposition to the next at a higher speed until the address of the selectedword is reached.

Since the track or shift register is formed as an integratedsemiconductor circuit, if a defect occurs in the semiconductor elementsassociated with any position on the track, the likelihood is very greatthat the data stored throughout the track will be erroneous becauseevery bit on the track would have to be circulated through the defectivepoint in order to complete one cycle. Such an erroneous track is knownas a stuck or inalterable track.

Because sequential access storage devices are extensively used asauxiliary storage apparatus associated with the control processing unitof a computer system, there is a need for an error-correcting system ofexpanded potential.

SUMMARY OF THE INVENTION Accordingly, it is a primary object of thepresent invention to provide an error-correction/detection system ofincreased potential to be used for checking parallel data produced bysequential access storage means containing a plurality of tracks.

It is another object of the present invention to provide such anerror-correction/detection system to be used on parallel data producedby a bank of semiconductor shift registers.

It is a further object of the present invention to provide such anerror-correction/detection system which is capable of distinguishingwhether the errors in the parallel binary data are produced by stucktracks or by other conditions.

It is yet another object of the present invention to provide such anerror-correction/detection system which has the capability of correctingerrors in data produced by stuck tracks in addition to correcting errorsin the data produced by other conditions.

The usefulness of the present invention is based upon the provision ofapparatus for effectively determining which of a plurality of cyclingdata tracks is in the stuck or inalterable condition. This isaccomplished by the novel expedient of inserting at a fixed position inthe cycling data track, a check bit which is the binary complement ofthe next preceding bit. Detecting means are associated with each cyclingdata track being read which sense a change in the binary state of databeing cycled in the track. The check bit and next preceding bit in thedata track are cycled past the detecting means; this is convenientlyaccomplished by putting the data track through one cycle, therebyinsuring the passage of the check bit and preceding bit through thedetecting means. Means are provided for indicating that the track is ina stuck condition in the absence of a detected change in the binarystate during such a cycle. In addition, means are provided for countingthe tracks in the stuck condition.

The expanded error-correction/detection capability of the correctionsystem of the present invention is achieved by a combination of theabove-described stuck track detection and counting means with means fordetecting the presence of an error condition in the parallel binary dataor word produced by a bank of tracks and for indicating a bit positionin said data pattern; this indicated bit position corresponds to theactual error in the data only when a single error is present in theparallel data. Such a single-error detecting means may be the customarysingle-error correction/detection Hamming code means. As will behereinafter explained in greater detail in the description, we havefound that single-error Hamming correction/detection means will onlypoint to the proper bit actually in error when only a single error ispresent in the parallel data pattern. If two or three errors arepresent, conventional Hamming code single-error correction/detectionwill never point to one of the actual errors, but rather will point to abit which is not in error. Also, it should be understood that anindication that a particular track is stuck does not alone indicatewhether the bit in the parallel data pattern produced by the stuck trackis in error, i.e., a stuck track is stuck either at a l binary bit or abit, and the bit at which the track is stuck may by chance be thecorrect one for the word.

Based in part upon these two properties, a correlation may be madebetween the particular track indicated to be stuck and the informationdetected by the Hamming code means which is the presence of an errorcondition and the indicated position alleged for the error. Such acorrelation involves means for determining if the indicated error by theHamming code means is coincident with a stuck track. The combinationfurther includes standard parity checking means for the binary datapattern which in combination with the Hamming code means, will indicatewhether an even number of errors are present in the binary pattern.Thus, the correlating means has the capability of correlating thedetected parity error, Hamming error condition, the indicated stucktrack and the count of stuck track with the presence or absence of acoincidence between a stuck track and a Hamming error in order tocorrect the errors either through means for complementing one or more ofthe stuck tracks or correcting a single Hamming error by conventionalmeans, or both.

As will be hereinafter described in greater detail, based upon thenature of the data pattern, it is possible to determine in advance whichcorrelated combination of parity error, bit error, coincident and stucktrack conditions and stuck track count should indicate particularsequences of stuck track complementing and Hamming error correcting inorder to expand the error-correcting capability and error-detectingcapability of the system with respect to the parallel binary datapattern being checked.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription and preferred embodiments of the invention as illustrated inthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a flow chart of anillustrative system embodying the present invention.

FIG. 2 is a layout sketch showing the relationship between FIGS. 2A and2B.

FIG. 2A is a diagram of the circuit logic used in indicating whichtracks are stuck.

FIG. 2B is a diagram of the circuit logic used in counting the stucktracks.

FIG. 2C is a circuit logic diagram of the means for introducing intoeach data track, the check bit which is the complement of the nextpreceding bit.

FIG. 3 is a diagram of the circuit logic involved in determining thepresence of a Hamming error in the parallel binary data pattern,checking the parity of the parallel binary data, correcting the Hammingerror, complementing the stuck tracks and in passing corrected data oruncorrected good data.

FIG. 4 is a circuit logic diagram showing in greater detail the meansfor correcting Hamming errors and for complementing stuck tracks as wellas the means for determining the coincidence of stuck tracks withHamming errors.

FIG. 5 is a table showing the Hamming code and parity check bit used toillustrate the embodiment of the invention shown in FIGS. 2, 3 and 4.

HG. 6 is a flow chart illustrating another embodiment of the system ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart of anembodiment of the system of the present invention illustrating how thecombination of detecting and correcting means of the present inventionsubstantially expand error detecting and correcting capability withrespect to parallel binary data produced by a plurality of cyclingtracks.

With reference to FIG. 1, the section of the flow chart shown orenclosed in dashed lines, shows the maximum capability of a single-errorcorrection/double-error detecting Hamming code system conventionallyused in the prior art for detection and correction of errors in parallelbinary data. This Hamming code system is essentially a single-errorcorrectin single-error detecting Hamming code system which includes aparity check bit to increase the capability to doubleerror detection.Following the dotted line in the first step, the conventional systemdetects whether there is an odd or an even number of Hamming errors orno Hamming errors. If there are no errors, the data is passed as good.If there is an odd number of errors, a condition which is determined bythe combination of a Hamming error indication plus a wrong parity check,it is assumed that there is one error present, and the error iscorrected and the data passed as good. If it is determined that thereare an even number of errors present, indicated by the combination of aHamming error condition plus a correct parity condition, it is assumedthat there is a double error present and the system is halted since itcan only detect and not correct such a condition.

On the other hand, the detection and correction system of the presentinvention has an expanded capability illustrated by the flow chart inFIG. 1 where the unbroken lines and enclosures indicate the detectionand correction steps possible with the present invention. The systemillustrating the present invention involves the following steps. First,a determination is made as to the number of stuck tracks. If there arethree or more stuck tracks, the operation is halted and an appropriatesignal given. Ifthere are less than three stuck tracks, a determinationis made as to the Hamming error condition. If there are an odd number ofHamming errors present as indicated by a combination of wrong parity andthe indication of a Hamming error, the assumption is not automaticallymade as in the prior art that there is only one error in the data andthe error pointed to by the Hamming code system corrected. Rather, adecision is first made as to whether there are two stuck tracks. Ifthere are not two stuck tracks, then the Hamming error pointed to iscorrected and the data passed as good. However, if there are two stucktracks present, then a determination is made as to whether the Hammingerror pointed to is coincident with one of the indicated stuck tracks.If there is such a coincidence, then that indicated Hamming error iscorrected and the data passed as good. On the other hand, if theindicated Hamming error is not coincident with one of the stuck tracks,the operation is halted and a signal given indicative of a faultcondition involving two stuck tracks plus an additional independentHamming error. In explanation as to why these decisions are made in thecase of two stuck tracks, first, if there are not two stuck tracks, thenthere are either none or one stuck track. If there are no stuck tracks,

then it can be safely assumed that there is one random error and thaterror is corrected. If there is one stuck track, it can also be safelyassumed that the indicated Hamming error is in the stuck track and thatHamming error is then corrected.

In following these operations, it should be understood that a stucktrack need not be in error; the track may be either stuck at a bit whichis correct for the particular parallel data, in which case that bitwould not show up as a Hamming error, or track may be stuck at a bitwhich is incorrect for the particular parallel data, in which case thatbit will show up as a Hamming error. For convenience, we can classifystuck tracks whether in error or not, as faults, and also classifyrandom or transient errors as faults.

With this in mind then, where there is an indication of two stuck tracksand the indicated Hamming error does not coincide with a stuck track,the system is halted and an appropriate signal given to the operatornoting the detection of a triple-fault condition including two stucktracks plus an additional random error. Conversely, if there are twostuck tracks and the indicated random error is pointing at a stuck track(indicating coincidence) then it may be correctly assumed that one ofthe tracks is stuck at an error condition for that particular data andthat a double-fault condition exists (two stuck tracks) which theapparatus can correct by correcting the indicated Hamming error and thenpassing the data as good.

Let us now consider the other branch of the flow chart. Where there isan indication of an even number of Hamming errors by virtue of thecombination of an indicated Hamming error plus a correct parity, then ifthis is the first pass in the system, all of the bits in the parallelbinary data pattern produced by stuck tracks are complemented. Anindication is made that the first pass is completed and the complementedparallel data is returned to the Hamming error detection means for adetermination as to whether the error condition has changed. Thefollowing possibilities may occur: the Hamming error condition maychange from even to odd, in which case it can be handled along the oddbranch of the flow chart as previously indicated; the Hamming errors maydisappear, in which case the data may be passed as good, or the Hammingerror condition may remain even, in which case since the first pass hasbeen completed as previously indicated, the system is then halted with asignal to the operator indicating the detection of two Hamming errorswhich cannot be corrected by complementing the stuck tracks.

With reference to the circuits shown in FIGS. 2A, 2B, 2C, 3 and 4, therewill now be described circuitry capable of implementing the flow chartshown in FIG. 1. For the purposes of this description the bank ofcycling data tracks providing the parallel binary data patterns or wordswill be a bank of shift registers formed as integrated semiconductorcircuits of the type described in previously mentioned copendingapplication Ser. No. 889,435, now U.S. Pat. No. 3,648,255 issued Mar.14, 1972. A bank of eight of these shift registers or tracks is shown inFIG. 2A. These eight tracks produce an eight-bit binary data pattern inwhich the groupings are coded in accordance with the single-errorcorrecting/double-error detecting code tabulated in FIG. 5. In thiscode, the first, second and fourth bits of the word are Hamming bits andthe eighth or P bit is a parity bit. There are four actual informationhits, the third, fifth, sixth and seventh bits. The eight-bit words havebeen selected primarily for convenience in description, and will beunderstood that the correction system of the present invention willapply to words of any length as long as there are sufficient bitspresent for the Hamming and parity checks.

The tracks shown each contain 256 bits of electronically cycling binarydata. Each of shift registers 10 may be any one of a number of knowndynamic shift registers for electronically cycled data. The details ofsuch shift registers are described on page 81 of an article by R. L.Petritz, entitled Current Status of Large-Scale Integration Technology,published in the 1967 Proceedings of the Fall Joint Computer Conference.One embodiment of such a shift register is described in copendingapplication Ser. No. 889,435, now

U.S. Pat. No. 3,648,255 issued Mar. 14, 1972. In such a shift register,the data stored must be periodically regenerated. This is done by meansof a high-speed clock operating in conjunction with a low-speed clock.During the inactive or storage cycle of the storage means or memorywhich is comprised by the bank of shift registers, the data stored inthe shift register is regenerated by low-speed cycling under the controlof the low-speed clock which periodicallyshifts each of the bits storedin each track to the next succeeding position. Then, during the activephase of the memory, when it is desired to remove a word of data fromacross a bank of cycling shift registers or tracks, the data in theregisters is cycled by shifting from one position to the next succeedingposition at a higher speed until the address of the selected word isreached. In FIG. 2A, we have not shown the highspeed or low-speedclocks. However, it is to be noted that shift pulse generator 11 whichprovides the shift pulses to the eight shift registers 10, isselectively controlled by either a low-speed clock or a high-speed clockto maintain the data stored in the registers circulating at either thelow-speed or the high-speed required by the particular storage stage.

Considering now the means for determining which tracks are stuck, eachtrack or shift register 10 in FIG. 2A contains a 257th or check bitimmediately succeeding the 256th bit. This check bit is the binarycomplement of the 256th bit. This check bit may be inserted into theshift register by a technique which involves inverting the binary valueof the 256th bit and putting this value into the 257th or check positionin the track. This may be accomplished during the work-up period whendata is initially loaded into the track 10. FIG. 2C shows a generalizedembodiment of circuitry for accomplishing this. As the shift register isbeing cycled by means of shift pulse generator 11, counting means 12counts the number of shift pulses and on the 256th pulse, provides asignal which activates read means 13 to read the binary bit in the 256thposition; the value of this bit is inverted by inverting means 14 andthe inverted value is reinserted into the track through write means 15through an appropriate delay 16 which insures that the write means 15will be activated coincident with the arrival of the 257th or checkposition at the write position. It is to be noted that there is a read13, write 15, invert l4 and delay 16 means associated with each of thetracks under the control of a single shift pulse generator 1 l andcounter 12.

Returning now to FIG. 2A, assume that tracks 10 are all cycling and thateach has a check bit which is the complement of the next proceeding or256th bit. During a given cycle, shift pulse counter 12 keeps track ofthe pulse count, and during the 256th and 257th pulses, applies a gatingsignal to each of gating terminals 17 of AND gates 18 of the stuck trackindicator circuit. Simultaneously with the application of the gatingsignal to terminal 17, the binary data in the 256th position followed bythe binary data in the check position will be applied to data terminal19 of the gate 18 associated with the particular track. The signalapplied to terminal 19 will be the standard up level for a binary I, anddown level for a binary 0." The resulting output from each of gates 18is applied to a binary trigger 20 respectively associated with each ofthe gates through terminal 21. All of the binary triggers 20 have beenpreviously reset to a value of binary 1. With this arrangement, it willbe seen that if the 256th and check bits in a given track are l and 0 orO and 1, then the output from the associated trigger 20 on outputtenninal 22 will be down or 0. This is the case because AND gate 18 willhave an up output on terminal 21 only once, thereby switching trigger 20and output 22 to the 0 binary value. On the other hand, if there are apair of 1's in the 256th and check positions, AND gate 18 will switchtrigger 20 twice, from 1 to 0 and back to l and out put 22 still remainat l; likewise, if there are a pair of 0s" in the 256th and checkpositions of a track AND gate 18 will produce no output and trigger 20will remain at 1. Thus, if track 10 is stuck, terminal 22 will be up,and if track 10 is not stuck, terminal 22 will be down. The output ofeach of terminals 22 is also applied to the corrector circuit associatedwith each track, shown in FIGS. 3 and 4 by means of line 23 as will behereinafter described in greater detail Considering now how the stucktrack count is obtained, the output terminals 22 from triggersassociated with each of the eight tracks are applied through eightcorresponding lines '24 to the counter circuit of FIG. 2B. This circuitprovides three distinct outputs: one output if three or more of lines 24are up, indicative of at least three stuck tracks; another output ifonly two of lines 24 are up, indicative of two stuck tracks; and a thirdoutput if none or one of lines 24 are up, indicative of a 0,1 stucktrack condition. The first two lines 24 from the first and second tracksare respectively connected to both OR gate 25 and AND gate 26 in themanner shown. If only one of these two first lines is up, only outputline 27 from OR gate 25 will be up; if both of these first two lines areup, then both line 27 and output line 28 from AND gate 26 will be up.Line 27 is connected to OR gate 29 and AND gate 30, while line 28 isconnected to OR gate 31 and AND gate 32. The output of AND gate is alsoapplied to OR gate 31. In turn, the line 24 indicative of the conditionof the third track, is connected to OR gate 29, AND gate 30, and ANDgate 32. From the circuitry involved, it follows that if at this pointonly one of the first three lines 24 is up, then only output line 33from OR gate 29 will be up. If two of these three lines are up, then,output line 34 from OR gate 31 will also be up. If all of the firstthree lines 24 are up, then, in addition to lines 33 and 34, output line35 from AND gate 32 will be up. Since an up output on line 33 ismaintained through the circuit via OR gates 29' through 29", output line36 will be up if at least one of the eight tracks is stuck. Likewise,since an up output on line 34 is maintained through the circuit via ORgates 31' through 31", if at least two of the eight tracks are stuck,line 37 will be up. As illustrated in the circuit, an up output on line28 or line 34, indicative of a stuck track count of at least two, willalso be applied to AND gates 32, 32' through 32". Since line 24 is alsoapplied to these AND gates, it follows that upon reaching a count ofthree lines 24 which are up after a count of two stuck tracks has beenmade, a particular one of AND gates 32 through 32" will be renderedconductive and the line 35 through 35" associated with this gate will beup and OR gate 38 will be conductive, bringing line 39 up to indicate acondition of three or more stuck tracks. The output on line 39 isinverted by inverter 40 and applied to AND gate 41; line 37 is alsoapplied to AND gate 41. In addition, the inverted output on line 39 isalso applied to AND gate 42. Also applied to AND gate 42 is the outputof AND gate 41 inverted by inverter 43.

Accordingly, as soon as the count of three or more stuck tracks appears,line 39 goes up and a signal is given to appropriate halting means 44 tohalt the apparatus. If the count is less than three stuck tracks, inputs45 and 46 respectively to AND gate 41 and 42 will both be up. Thus, ifthere are two stuck tracks, the input in line 37 to gate 41 will also beup, and when the appropriate gating signal is applied to terminal 47,the output 48 of AND gate 41 will be up, while the inverted input togate 42 will be down. On the other hand, if there are either none or onestuck back, line 37 will be down, line 48 will be down and the invertedinput to gate 42 will be up. When an appropriate gating signal isapplied to terminal 49 of gate 42, output 50 will then go up to indicate0,1 stuck tracks. It should be noted that while not needed in the flowchart shown in FIG. 1, if an indication of one stuck track asdistinguished from 0 stuck tracks is needed, it may be taken from line36 which should be up for the one stuck track condition.

With reference to FIG. 3, there will now be described the operation ofthe Hamming error and parity error detection means. The parallel binarydata to be examined for the Hamming and parity error is applied alongeight lines 51 through 51" with each of the lines corresponding to thedata in one of the eight tracks. Line 51 will be up for a binary 1" anddown for a binary 0." Each of the lines are applied to an Exclusive ORgate 52, each associated with the corrector S3 for the data in theparticular track. Since there is no corrections as yet, the data on line51 will be passed unchanged by the Exclusive OR gate as an output online 54. Each of lines 54 are applied to parity checker 55 respectively,via eight terminals 56 through 56". The parity checker 55 contains atree of Exclusive OR gates 57 to which the inputs are paired in themanner shown to provide an up or binary I level on output line 58in thepresence of an odd number of errors in the data pattern, and a downlevel on line 58 in the case of no errors or an even number of errors inthe data pattern. The parity check is an even parity check. In order todetect the Hamming errors, lines 54 are applied to Exclusive OR gatetrees 59, 60 and 61 in the following arrangement:

the lines corresponding to the first, third, fifth and seventh datatrack bits are applied to Exclusive OR tree 59;

the lines corresponding to the second, third, fifth, and sixth data bitsare applied to Exclusive OR tree 60; and

the lines corresponding to the fourth, fifth, sixth and seventh databits are applied to Exclusive OR tree 61.

This arrangement is a conventional arrangement for detecting by Hammingcode, the bit position of one error. This provides the single Hammingerror detecting means for the code in the words of the table in FIG. 5.In the absence of an error, output lines 62, 63 and 64 will be at binaryO. However, if an error is present, one or more of lines 62, 63 and 64will be a binary l The combination of lines 62, 63 and 64 which are at abinary 1 will be indicative of the bit position which is in error. Inorder to determine this bit position, line 62 is assigned the value ofl, line 63 is assigned the value of 2" and line 64 is assigned the valueof 4. Accordingly, if lines 62, 63 and 64 are in the combined 100"binary state, the total value will be I and this will indicate an errorin the first bit position corresponding to the first track. Likewise, ifthe combined value at 62, 63 and 64 is I01 this will add up to a totalvalue of 5, indicative of an error in the fifth bit position. If thecombined value is I 11, this will be indicative of an error in theseventh bit position. Decoder 65, to which lines 62, 63 and 64 areapplied, is a standard decoding means for decoding the combined binarystate of lines 62, 63 and 64 in accordance with the values set forthabove and providing an up" output on only one of the lines 66, each ofwhich is respectively connected to one of the correctors 53 associatedwith one of the data tracks as will be hereinafter described in greaterdetail. Lines 66 are referred to as Hamming error pointers because an upvalue on line 66 is only applied and thus points to the correctorassociated with the bit indicated to be in error. In this manner, thestandard single-error Hamming code detection is achieved.

At this point the apparatus only indicates that a Hamming errorcondition exists and an alleged error position is pointed to by one oflines 66. Now, in order to determine whether more than one error mayexist and whether the Hamming error condition is odd or even, theHamming error detection information must be coordinated with theinformation obtained from parity checker 55. This is accomplished asfollows. Lines 62, 63 and 64 are respectively connected to OR gate 67 bymeans of lines 68, 69 and 70. If one or more of lines 62, 63 and 64 areup, indicative of the presence of a Hamming error, OR gate 67 willproduce an up output on line 71 which will be respectively applied to ORgate 72 and AND gate 73 by means of input lines 74 and 75. Line 58 fromthe parity checker, which has been described as being up in the presenceof a parity error and down in the absence of a parity error, is alsoapplied to OR gate 72 via input line 76, and the binary level on line 58is inverted by inverter 77 and applied to AND gate 73 by line 78. SinceOR gate 72 may be activated by either a Hamming error or a parity error,in the absence of both types of error, OR gate 72 will benon-conductive, the output on line 79 will be down and consequently, theoutput on line 81 from inverter will be up. On the other hand, in thecase where there is a Hamming error condition but no parity error, bothinputs 75 and 78 to AND gate 73 will be up and the gate will be renderedconductive, bringing line 82 up to indicate an even number of errors.

Thus, an up" output on a respective one of lines 82, 81 or 58 willrespectively indicate the none," odd or even" branches from the Hammingerror decision box in the flow chart of FIG. 1.

If line 81 is up, lines 82 and 58 will be down. An up signal on line 81will be applied to OR gate 83 in FIG. 4 which in turn will produce thesignal to appropriate means for passing the parallel binary data as gooddata.

Considering now the implementing of the odd Hamming error branch in theflow chart of FIG. 1, when there are an odd number of errors, line 58 inFIG. 3 will be up, while lines 81 and 82 will be down. The value of line58 is applied via line 84 to each of the eight correctors 53 associatedwith each of the eight data bit lines 51 through 51". With reference toFIG. 4, there is shown a more detailed view of a corrector unitcircuitry. Line 84 is applied to AND gate 83 in each of the correctorunits 53. Also applied to each of AND gates 83 is line 85 from OR gate86. Simultaneously, an up level on line 84 which is also connected togating terminals 47 and 49 in gates 41 and 42 of the stuck track countershown in FIG. 2B, results in either line 48 or 50 being up, dependentrespectively on whether there are two stuck tracks or 0,1 stuck track.Since lines 48 and 50 are applied to OR gate 86, as shown in FIG. 4, ORgate 86 will be activated. In either case, line 85 which is applied toAND gate 83 will be up in the presence of two or less stuck tracks.Since both inputs 84 and 85 to all of the AND gates 83 are up, and onlythe Hamming error pointer line 66 to the AND gate 83 in the correctorassociated with the data track bit indicated to be in error is also up,gate 83 will be turned on only in the corrector associated with the databit indicated to have a Hamming error. In this corrector, output line 87will go up, rendering OR gate 88 active; this will apply an up input online 89, which is applied to Exclusive OR gate 52, the gate to which thedata bit binary level is also applied via line 51. Such an up input online 89 will cause Exclusive OR gate 52 to reverse the binary leveloutput on line 54 to the opposite binary level from that applied oninput line 51. Therefore, the binary level on line 54 will represent thecorrect bit binary level of the bit indicated to be in error. On all theother tracks, there will be no such up input on line 89 as a result ofthe Hamming error correction, and consequently, the binary level on line54 will remain unchanged from that on line 51.

If there are not two stuck tracks, i.e., 0,1 stuck tracks, then the upsignal on line 50 is applied by means of line 90 through delay means 91to OR gate 83 to activate OR gate 83 to provide the up signal on line 92which is then transmitted to means (not shown) which pass the correcteddata as good. This represents No branch of the two stuck track decisionblock shown in FIG. 1. Delay means 91 insures that there is sufficienttime for the data bit indicated to be in error, to be corrected by meansof Exclusive OR gate 52 prior to the pass signal being given on line 92.

Let us now consider the implementation of the Yes branch of the twostuck track decision block in FIG. 1. In addition to being applied to ORgate 86, an up level on line 48 indicative of two stuck tracks is alsoapplied via line 93 to one input of AND gate 94. The other input 95 toAND gate 94 will only be activated if there is a coincidence between thedata bit indicated to be in error and the stuck track, i.e., the bitindicated to be in error by the Hamming means is also on a trackindicated to be stuck. This is achieved as follows. Lines 23 from eachof the stuck track indicator triggers are applied to each of AND gates96 in each of the corrector units via input 97; if the track is stuck,line 23 and consequently, input 97 will be up. Also, output line 87 fromAND gate 83 is connected to AND gate 96 through line 98. Accordingly,since line 87 is up only in the one corrector unit associated with thebit having the indicated Hamming error, input line 98 will also be up inthat corrector. If the track providing the bit in error is stuck, line97 will also be up and consequently, AND gate 96 will be activated toprovide an up signal on line 99, applied to OR gate 100. Thus, thecoincidence of a stuck track and an indicated Hamming error in any oneof the data track bits in the parallel data, the line 99 associated withthat bit will be up and OR gate 100 will be activated to produce an uplevel on input line to AND gate 94. Since there are two stuck tracks,the other input 93 to AND gate 94 will also be up and AND gate 94 willbe activated. This will produce an up level on input 101 to OR gate 83which will activate OR gate 83, and the corrected data will be passed asgood. Simultaneously, input 102 to Exclusive OR gate 103 will be up. Inaddition, since there are two stuck tracks, input 104 to Exclusive ORgate 103, will also be up. In the presence of two up inputs, ExclusiveOR gate 103 will remain inactive and halt signal line 105 will be down.It should be noted that when embodying this Exclusive OR circuitry,Exclusive OR gate 103 has inputs which can be adversely effected by raceconditions. For example, where inputs 102 and 104 are to be up, thearrival of an up input on 102 before the arrival of the up input on 104may cause halt signal line 105 to momentarily go up. In order to avoidhalting on such a transient up signal, the halting means may beassociated with the timing means which does not determine the haltcondition until the inputs to gate 103 have had time to stabilize.

However, if there is no coincidence between a stuck track and a Hammingerror in the particular hit, all of lines 99 will be down, OR gate willbe inactive, line 95 will be down, AND gate 94 will be inactive andlines 101 and 102 will be down. Accordingly, OR gate 83 will be inactiveand there will be no up signal on the pass data line 92. On the otherhand, since there are two stuck tracks, input line 104 will be the onlyinput to Exclusive OR gate 103 which will be up. This will activateExclusive gate 103 and output line will be up to provide the signalwhich will be applied to appropriate means for halting the apparatus.

In the previous discussion with respect to the flow chart, we gave thereason for making the various decisions involved. At this point, we willelaborate as to why decision is made to halt the system when there is acombination of two stuck tracks, an indicated Hamming error, but theindicated Hamming error is not coincident with one of the stuck tracks.We have discovered that by the very nature of Hamming code errordetection, i.e., the parallel binary data pattern is broken down into aplurality of sub-groupings each of which contains one Hamming check bit,and the Hamming parity of each subgrouping is checked by means one ofExclusive OR trees 59, 60 or 61 in FIG. 3, the bit indicated to be inerror is the bit actually in error only if there is one error present.In other words, if two or three bits in the data pattern are in error,the bit indicated or pointed to by this Hamming code detection means tobe in error will actually be a bit which is correct. Therefore, if anattempt is made to change'the bit which is already correct, the errorcondition will only be compounded.

Accordingly, where there are two stuck tracks and the indicated Hammingerror does not coincide with the stuck track, two situations couldproduce such a combination:

1. two stuck tracks which are stuck at the correct bit for theparticular data pattern being considered plus an error in a bit not on astuck track; or

2. two stuck tracks at least one of which is stuck at a bit actually inerror for the data pattern, plus additional possible error or errors inother data bits which produce a Hamming code indication or point at abit not actually in error as a result of the multiple error condition.

Because the second possible condition is incorrectible, and even in thecase of the first condition, we have a triple fault condition whichmakes it quite risky to continue, the system is halted so thatappropriate correction can be made manually.

Considering now the implementation of the Even (parity correct pluserror condition) branch of the Hamming error decision box in FIG. 1,which is implemented by apparatus shown in FIG. 3. Ifthere are an evennumber of errors, line 82 will be up and, consequently, input 106 to ANDgate 107 will be up. Since this is the first pass through the circuit,first pass latch 108 has been set or reset by the previous applicationof an appropriate signal to reset terminal 109; this reset signal mayconveniently be a timed up pulse applied coincidently with theapplication of the parallel data pattern to the Hamming error detectionmeans. Consequently, output terminal 110 will be up and the other input111 to AND gate 107 will be up, thereby activating AND gate 107 to bringline 112 up. This causes the application of an up level to complementlatch 113 which has been previously set or reset via terminal 114 by thesame timed pulse which reset latch 108 so that an up level on line 112will produce an up output on line 115 from latch l 13. Line 1 is appliedto AND gate 116 in each of the corrector units shown in FIG. 4. In theAND gates 116 in correctors associated with tracks which are stuck, theother input from line 23 will also be up, resulting in the activation ofAND gate 1 16 to produce an up level on line 117 and thereby activate ORgate 88 which in turn, brings input 89 to Exclusive OR gate 52 up. Thiscauses Exclusive OR gate 52 to produce on line 54, the complement orreverse of the binary state of the data bit applied via line 51.

The data on lines 54, including the complemented data from stuck tracks,is still applied to Exclusive OR trees 59, 60 and 61 of the Hammingerror detector as well as to parity checker 55, in the manner which hasbeen previously described. [f the complementing of the stuck track hasresulted in a change in the Hamming error condition, line 82 which hasbeen up, should go down and either line 81 or line 84 should come up. Ifline 81 comes up, the complementing procedure has corrected all errors;no errors are present and the corrected data is passed as good. If line84 comes up, then the complementing of the stuck track has resulted inthe change from an even error condition to an odd error condition, andthis odd error condition is then handled in accordance with the oddbranch of the error decision box, the implementation of which has beenpreviously described.

On the other hand, the complementing of the stuck track may fail tochange the Hamming error condition, in which case line 82 will remainup. The previously mentioned up level on line 1 12, which was applied tocomplement latch 113, has also been applied to delay means 118, thefunction of which is to provide a delay sufficient for the describedcomplementing steps to take place and the new error condition tostabilize. Thus, upon the completion of the complementing step, the uplevel from line 112 is applied to first pass latch 108 via line 119.This brings line 110 down, shutting AND gate 107 off. The output on 110is inverted through inverter 120 to bring input terminal 121 of AND gate122 up. Since the other input to AND gate 122 from line 82 remains up,the gate is activated and line 123 is brought up to signal appropriateapparatus to halt the system.

The embodiment previously described is intended to illustrate how inaccordance with the present invention, the combination of parity error,Hamming bit error, coincident condition, stuck track condition and stucktrack count may be correlated to detect and/or correct parallel binarydata when predetermined combinations of said conditions occur. Theprimary advantage of the present invention is not so much to teach thevaried combinations of said conditions which may be respectivelyresponded to by various detection and/or correction procedures but,rather, the present invention provides the means for detenmining andcorrelating the conditions.

It should be understood that, at the present time, the capability ofembodiments of the present invention does not go beyond the consistenthandling of triple-fault and/or tripleerror conditions. In other words,if there are four faults, and particularly four Hamming type errors, theembodiments of the present invention are not capable of handling such acondition with any consistency. This is, to a great extent, due tolimitations in the Hamming code. It can be foreseen that if commerciallypractical Hamming codes circuitry is developed which goes beyond thedouble detect/single correct capability of present Hamming codescircuitry, the combination of the present invention will still furtherextend the capabilities of systems containing such Hamming codecircuitry.

In order to illustrate that the information detected and correlated inthe previously illustrated embodiment of the present invention may beresponded to with a different detection/correction procedure, FIG. 6illustrates a system for handling the 5 Even branch of the Hamming errordecision box illustrated in FIG. 1. In this Even branch, on the firstpass, a decision is made as to whether only two tracks are stuck. Ifthat decision is No, the stuck track is complemented, the first passindicator is set as previously described, and the complemented data isagain subjected to the Hamming error decision means in the mannerillustrated with respect to FIG. 1. On the other hand, if two stucktracks are present, a decision is made as to whether the bit indicatedby the Hamming means to be in error, coincides with a stuck track. Ifthat decision is No, the

1 procedure of complementing all of the stuck tracks and recycling thedata to the Hamming error decision means, is carried out. On the otherhand, if the bit indicated by the Hamming means to be in error, doescoincide with the stuck track, only the other stuck track iscomplemented and the complemented data recycled to the Hamming errordecision means as previously described. The basis for this decision isthat since there are an even number of errors present, there must bemore than one Hamming error. As we have previously indicated, in thepresence of two or three Hamming errors, the Hamming error indicatingmeans does not point to a bit actually in error, but points to a correctbit. Accordingly, the stuck track which coincides to the bit pointed toby the Hamming means must be stuck at a correct bit condition and neednot be complemented. Otherwise, if all of the stuck tracks werecomplemented whatever error might have been corrected in the stucktracks not pointed to, would only be reintroduced into the stuck trackpointed to since that track is already at a correct bit.

35 It should be noted that because the circuitry in the illustrativeembodiments of the present invention is digital or nonlinear incharacteristic, for convenience in description, the terms up and downhave been used to describe the binary states of various pointsthroughout the circuit; up" should be considered as equivalent to abinary l and down" should be considered to be equivalent to a binary 0.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is: 1. Apparatus for detecting errors in a parallelbinary data pattern made of a plurality of binary bits, each of saidbits being respectively produced by one of a plurality of data trackscomprising means for receiving the bits produced by said tracks anddetecting which tracks are in an inalterable condition;

means receiving the parallel data pattern for detecting the presence ofbit error condition in said binary data and for indicating the properbit position in said data pattern of an error only when a single erroris present in said pattern;

means responsive to said two previous means for determining if saidindicated bit error is coincident with a track determined to be in aninalterable condition.

2. The apparatus of claim 1 wherein each of the tracks comprises cyclingsequential binary data bits containing at least one check bit which isthe binary complement of the next preceding bit, and

said means for detecting which tracks are in an inalterable conditioncomprise:

means for detecting a change in the binary state in each of said cyclingdata tracks means for cycling said tracks so that each of said checkbits and next preceding bits pass said detecting means, and

means responsive to each of said detecting means for indicating that thetrack corresponding to the detecting means is in an inalterablecondition in the absence of a detected change.

3. The apparatus of claim 1 wherein said error detecting and indicatingmeans are Hamming Error detecting means.

4. The apparatus of claim 1, further including means associated withsaid inalterable track detecting means for counting the inalterabletracks, means receiving the parallel data pattern for detecting thepresence of a parity error in the binary data pattern,

means responsive to said parity error-detecting means, biterror-detecting means, coincidence determining means, said inalterabletrack detecting means and said inalterable track counting means forcorrelating said detected parity error, bit error, coincident andinalterable track conditions with said inalterable track count, and

complementing means responsive to said correlating means for selectivelycomplementing bits produced by at least one of said inalterable trackswhen said correlated conditions and count correspond to a predeterminedcombination of said conditions and count.

5. The apparatus of claim 4 wherein each of the tracks comprises cyclingsequential binary data bits containing at least one check bit which isthe binary complement of the next preceding bit, and

said means for detecting which tracks are in an inalterable conditioncomprise:

means for detecting a change in the binary state in each of said cyclingdata tracks means for cycling said tracks so that each of said checkbits and next preceding bits pass said detecting means, and

means responsive to each of said detecting means for indicating that thetrack corresponding to the detecting means is in an inalterablecondition in the absence of a detected change. 6. The apparatus of claim1, further including means associated with said inalterable trackdetecting means for counting the inalterable tracks,

means receiving the parallel data pattern for detecting the presence ofa parity error in the binary data pattern,

means responsive to said parity error-detecting means, biterror-detecting means, coincidence determining means, said inalterabletrack detecting means and said inalterable track counting means forcorrelating said detected parity error, bit error, coincident error andinalterable track conditions with said inalterable track count, and

correcting means responsive to said correlating means for selectivelycorrecting said indicated bit position error when said correlatedconditions and count correspond to a predetermined combination of saidconditions and count.

7. The apparatus of claim 6 wherein said bit error detecting andindicating means are Hamming Error detecting means and said means forcorrecting said indicated bit position error are Hamming Errorcorrection means.

8. The apparatus of claim 6 further including complementing meansresponsive to said correlating means for selectively complementing bitsproduced by at least one of said inalterable tracks when said correlatedconditions and count correspond to a predetermined combination of saidconditions and count.

9. The apparatus of claim 6 wherein said correcting means respond to apredetermined combination with a count of two.

10. The apparatus of claim 8 wherein said correcting means respond to apredetermined combination with a count of two.

11. The apparatus of claim wherein said complementing means respond to apredetermined combination in which there is a bit error condition and noparity error.

12. The apparatus of claim 8 wherein said complementing means respond toa predetermined combination in which there is a bit error condition andno parity error.

13. The apparatus of claim 4 wherein said complementing means respond toa predetermined combination in which there is a bit error condition, noparity error, two inalterable tracks and a coincident condition, and

said complementing means complement only the inalterable track which isnot coincident with said indicated random error bit position.

14. The apparatus of claim 13 wherein said error detecting andindicating means are Hamming Error detecting means.

15. The apparatus of claim 8, further including means responsive to saidinalterable track counting means for halting the apparatus when thecount of inalterable tracks is at least three.

16. The apparatus of claim 1 wherein each of said tracks is a shiftregister.

17. The apparatus of claim 8 wherein each of said tracks is a shiftregister.

18. The apparatus of claim 16 wherein said shift registers areintegrated semiconductor circuits.

19. The apparatus of claim 17 wherein said shift registers areintegrated semiconductor circuits.

20. Apparatus for detecting and correcting errors in a parallel binarydata pattern made of a plurality of binary bits, each of said bits beingrespectively produced by one of a plurality of data tracks comprisingmeans for receiving the bits produced by said tracks and determiningwhich tracks are in an inalterable condition;

means associated with said inalterable track determining means forcounting the number of tracks in said inalterable condition;

means responsive to said inalterable track counting means for haltingthe apparatus when the count of inalterable tracks is at least three;

first detecting means receiving the parallel data pattern for detectingthe presence of a parity error in the parallel binary data pattern;

second detecting means receiving the parallel data pattern for detectingthe presence of a bit error condition in said binary data and forindicating one of the bits in said data pattern, said indicated bitbeing in error only when there is a single error in said binary datapattern;

means for applying said binary data pattern to said first and seconddetecting means;

means, responsive to said first and second detecting means and saidinalterable track determining means and activated by the combination ofthe absence of a parity error and the presence of a bit error conditionin the applied data pattern, for complementing the bits in said paralleldata pattern produced by tracks in inalterable condition;

means for reapplying said complemented data pattern produced by saidcomplementing means to said first and second detecting means;

means responsive to said first and second detecting means for providingan error output signal if said reapplied complemented data pattern stillresults in the combinations of the absence of a parity error and thepresence of an error condition;

means responsive to said first and second detecting means for passingthe original or reapplied data pattern as a good pattern in the absenceof both said parity error and error condition;

means, responsive to said first and second detecting means and saidinalterable track counting means and activated by the combination of thepresence of a parity error and an indicated bit error in the original orreapplied data pattern and an inalterable track count of less than two,for correcting said indicated bit error and for passing the correcteddata pattern as a good pattern;

means, responsive to said inalterable track determining means and saidbit error detecting means, for determining if said indicated bit erroris coincident with a stuck track; and

means, responsive to said first and second detecting means,

said inalterable track counting means, coincidence determining means andsaid inalterable track determining means and activated by thecombination of the presence of a parity error and an indicated bit errorin the original or reapplied data pattern and an inalterable track countof two for correcting said indicated bit error and for passing thecorrected data pattern if said indicated bit error is coincident with astuck track, or

for providing an error output signal if said indicated bit error is notcoincident with a stuck track.

21. The apparatus of claim wherein each of said data tracks is a shiftregister.

22. The apparatus of claim 20, wherein said second detecting means areHamming Error detection means and said means for correcting theindicated bit error are Hamming Error correction means.

23. The apparatus of claim 21 wherein said shift register is anintegrated semiconductor circuit.

24. The apparatus of claim 20 wherein at least one of said means forproviding an error output signal also halts the apparatus upon providingsaid error signal.

25. Apparatus for detecting whether a track of cycling sequential binarydata bits is in an inalterable condition comprising means forcomplementing one of said bits in said track and for inserting saidcomplemented bit into said track as a check bit,

means for detecting a change in the binary state in said cycling datatrack, means for cycling said track so that said check bit and itscorresponding original bit pass said detecting means, and

means responsive to said detecting means for indicating that the trackis in an inalterable condition in the absence of said detected change.

26. The apparatus of claim 25, wherein the entire data track is cycledpast said detecting means, thereby insuring that the check bit and theoriginal bit will be cycled past said detecting means.

27. The apparatus of claim 25 wherein said detecting and indicatingmeans comprise a bistable circuit to which said check bit and saidoriginal bit are sequentially applied, the output state of said bistablecircuit indicating whether there has been a change in binary statebetween said two applied bits.

28. The apparatus of claim 25 wherein said original bit passes saiddetection means immediately preceding said check bit.

29. Apparatus for detecting whether any of a plurality of tracks ofcycling sequential binary data bits are in an inalterable conditioncomprising means for complementing one of said bits in each of saidplurality of tracks and for inserting each of said complemented bitsrespectively into said plurality of tracks as check bits,

means for detecting a change in the binary state in each of said cyclingdata tracks, means for cycling said tracks so that each of said checkbits and their original bits pass said detecting means, and

means responsive to each of said detecting means for indicating that thetrack corresponding to the detecting means is in an inalterablecondition in the absence of a detected change.

30. The apparatus of claim 29 wherein each of said original bits passesits respective detection means immediately preceding its respectivecheck bit in each of said tracks.

31. A method for detecting errors in parallel binary data made of aplurality of binary bits, each of said bits being respectively producedby one of a plurality of data tracks comprising l detecting which tracksare in an inalterable condition;

by a single error Hamming Code Detection method, detecting the presenceof a bit error condition in said binary data and indicating the properbit position in said data pattern of an error only when a single erroris present in said pattern, and

determining if said indicated random error is coincident with a trackdetermined to be in an inalterable condition.

32. The method of claim 31, further including the steps of counting theinalterable tracks,

detecting the presence of a parity error in the binary data pattern,

correlating said detected parity error, bit error, coincident andinalterable track conditions with said inalterable track count, and

selectively complementing bits produced by at least one of saidinalterable tracks when said correlated conditions and count correspondto a predetermined combination of said conditions and count.

33. The method of claim 31, further including the steps of counting theinalterable tracks,

detecting the presence of a parity error in the binary data pattern,

correlating said detected parity error, bit error, coincident error andinalterable track conditions with said inalterable track count, and

selectively correcting said indicated Hamming error when said correlatedconditions and count correspond to a predetermined combination of saidconditions and count.

34. The method of claim 33, further including the step of selectivelycomplementing bits produced by at least one of said inalterable trackswhen said correlated conditions and count correspond to a predeterminedcombination of said conditions and count.

35. The method of claim 34 wherein said selective correction is madewhen said predetermined combination includes a count of two.

36. The method of claim 32 wherein said selective complementing is madewhen said predetermined combination includes a bit error condition, noparity error, two inalterable tracks and a coincident condition, and

only the inalterable track which is not coincident with said indicatedrandom error bit position is complemented.

37. A method for detecting and correcting errors in a parallel binarydata pattern made of a plurality of binary bits, each of said bits beingrespectively produced by one of a plurality of data tracks comprisingdetermining which tracks are in an inalterable condition;

counting the number of tracks in said inalterable condition;

halting the apparatus when the count of inalterable tracks is at leastthree;

detecting the presence of a parity error in the parallel binary datapattern;

by a single error Hamming Code Detection method detecting the presenceof an error condition in said binary data and indicating one of the bitsin said data pattern, said indicated bit being in error only when thereis a single error in said binary data pattern,

applying said binary data pattern to said first and second detectingmeans; upon the combination of the absence of a parity error and thepresence of an error condition in the applied data pattern, thencomplementing the bits in said parallel data pattern produced by tracksin inalterable condition;

reapplying said complemented data pattern to said first and seconddetecting means; signaling an error if said reapplied complemented datapattern still results in the combination of the absence of a parityerror and the presence of an error condition;

passing the original or reapplied data pattern as a good pattern in theabsence of both said parity error and error condition;

upon the combination of the presence of a parity error in the originalor reapplied data pattern and an inalterable track count of less thantwo, then correcting said indicated bit error and for passing thecorrected data pattern as a good pattern;

determining if said indicated bit error is produced by a stuck track,and

upon the combination of the presence of a parity error in the originalor reapplied data pattern and an inalterable track count of two, thencorrecting said indicated bit error and for passing the corrected datapattern if said indicated bit error is produced in a stuck track, or

providing an error output signal if said indicated bit errorinserting'into the track, at least one check bit which is the is notproduced by a stuck track. binary complement of the next preceding bit,and 38. A method for detecting whether a track of cycling deteFtingWhether there is f change in h binary Slate in sequential binary databits is in an inalterable condition comcyclmg data u'ack dunng one cycleof i i n n- 1- h u

1. Apparatus for detecting errors in a parallel binary data pattern madeof a plurality of binary bits, each of said bits being respectivelyproduced by one of a plurality of data tracks comprising means forreceiving the bits produced by said tracks and detecting which tracksare in an inalterable condition; means receiving the parallel datapattern for detecting the presence of bit error condition in said binarydata and for indicating the proper bit position in said data pattern ofan error only when a single error is present in said pattern; meansresponsive to said two previous means for determining if said indicatedbit error is coincident with a track determined to be in an inalterablecondition.
 2. The apparatus of claim 1 wherein each of the trackscomprises cycling sequential binary data bits containing at least onecheck bit which is the binary complement of the next preceding bit, andsaid means for detecting which tracks are in an inalterable conditioncomprise: means for detecting a change in the binary state in each ofsaid cycling data tracks means for cycling said tracks so that each ofsaid check bits and next preceding bits pass said detecting means, andmeans responsive to each of said detecting means for indicating that thetrack corresponding to the detecting means is in an inalterablecondition in the absence of a detected change.
 3. The apparatus of claim1 wherein said error detecting and indicating means are Hamming Errordetecting means.
 4. The apparatus of claim 1, further including meansassociated with said inalterable track detecting means for counting theinalterable tracks, means receiving the parallel data pattern fordetecting the presence of a parity error in the binary data pattern,means responsive to said parity error-detecting means, biterror-detecting means, coincidence determining means, said inalterabletrack detecting means and said inalterable track counting means forcorrelating said detected parity error, bit error, coincident andinalterable track conditions with said inalterable track count, andcomplementing means responsive to said correlating means for selectivelycomplementing bits produced by at least one of said inalterable trackswhen said correlated conditions and count correspond to a predeterminedcombination of said conditions and count.
 5. The apparatus of claim 4wherein each of the tracks comprises cycling sequential binary data bitscontaining at least one check bit which is the binary complement of thenext preceding bit, and said means for detecting which tracks are in aninalterable condition comprise: means for detecting a change in thebinary state in each of said cycling data tracks means for cycling saidtracks so that each of said check bits and next preceding bits pass saiddetecting means, and means responsive to each of said detecting meansfor indicating that the track corresponding to the detecting means is inan inalterable condition in the absence of a detected change.
 6. Theapparatus of claim 1, further including means associated with saidinalterable track detecting means for counting the inalterable tracks,means receiving the parallel datA pattern for detecting the presence ofa parity error in the binary data pattern, means responsive to saidparity error-detecting means, bit error-detecting means, coincidencedetermining means, said inalterable track detecting means and saidinalterable track counting means for correlating said detected parityerror, bit error, coincident error and inalterable track conditions withsaid inalterable track count, and correcting means responsive to saidcorrelating means for selectively correcting said indicated bit positionerror when said correlated conditions and count correspond to apredetermined combination of said conditions and count.
 7. The apparatusof claim 6 wherein said bit error detecting and indicating means areHamming Error detecting means and said means for correcting saidindicated bit position error are Hamming Error correction means.
 8. Theapparatus of claim 6 further including complementing means responsive tosaid correlating means for selectively complementing bits produced by atleast one of said inalterable tracks when said correlated conditions andcount correspond to a predetermined combination of said conditions andcount.
 9. The apparatus of claim 6 wherein said correcting means respondto a predetermined combination with a count of two.
 10. The apparatus ofclaim 8 wherein said correcting means respond to a predeterminedcombination with a count of two.
 11. The apparatus of claim 5 whereinsaid complementing means respond to a predetermined combination in whichthere is a bit error condition and no parity error.
 12. The apparatus ofclaim 8 wherein said complementing means respond to a predeterminedcombination in which there is a bit error condition and no parity error.13. The apparatus of claim 4 wherein said complementing means respond toa predetermined combination in which there is a bit error condition, noparity error, two inalterable tracks and a coincident condition, andsaid complementing means complement only the inalterable track which isnot coincident with said indicated random error bit position.
 14. Theapparatus of claim 13 wherein said error detecting and indicating meansare Hamming Error detecting means.
 15. The apparatus of claim 8, furtherincluding means responsive to said inalterable track counting means forhalting the apparatus when the count of inalterable tracks is at leastthree.
 16. The apparatus of claim 1 wherein each of said tracks is ashift register.
 17. The apparatus of claim 8 wherein each of said tracksis a shift register.
 18. The apparatus of claim 16 wherein said shiftregisters are integrated semiconductor circuits.
 19. The apparatus ofclaim 17 wherein said shift registers are integrated semiconductorcircuits.
 20. Apparatus for detecting and correcting errors in aparallel binary data pattern made of a plurality of binary bits, each ofsaid bits being respectively produced by one of a plurality of datatracks comprising means for receiving the bits produced by said tracksand determining which tracks are in an inalterable condition; meansassociated with said inalterable track determining means for countingthe number of tracks in said inalterable condition; means responsive tosaid inalterable track counting means for halting the apparatus when thecount of inalterable tracks is at least three; first detecting meansreceiving the parallel data pattern for detecting the presence of aparity error in the parallel binary data pattern; second detecting meansreceiving the parallel data pattern for detecting the presence of a biterror condition in said binary data and for indicating one of the bitsin said data pattern, said indicated bit being in error only when thereis a single error in said binary data pattern; means for applying saidbinary data pattern to said first and second detecting means; means,responsive to said first and second detecting means and said inalterabletracK determining means and activated by the combination of the absenceof a parity error and the presence of a bit error condition in theapplied data pattern, for complementing the bits in said parallel datapattern produced by tracks in inalterable condition; means forreapplying said complemented data pattern produced by said complementingmeans to said first and second detecting means; means responsive to saidfirst and second detecting means for providing an error output signal ifsaid reapplied complemented data pattern still results in thecombinations of the absence of a parity error and the presence of anerror condition; means responsive to said first and second detectingmeans for passing the original or reapplied data pattern as a goodpattern in the absence of both said parity error and error condition;means, responsive to said first and second detecting means and saidinalterable track counting means and activated by the combination of thepresence of a parity error and an indicated bit error in the original orreapplied data pattern and an inalterable track count of less than two,for correcting said indicated bit error and for passing the correcteddata pattern as a good pattern; means, responsive to said inalterabletrack determining means and said bit error detecting means, fordetermining if said indicated bit error is coincident with a stucktrack; and means, responsive to said first and second detecting means,said inalterable track counting means, coincidence determining means andsaid inalterable track determining means and activated by thecombination of the presence of a parity error and an indicated bit errorin the original or reapplied data pattern and an inalterable track countof two for correcting said indicated bit error and for passing thecorrected data pattern if said indicated bit error is coincident with astuck track, or for providing an error output signal if said indicatedbit error is not coincident with a stuck track.
 21. The apparatus ofclaim 20 wherein each of said data tracks is a shift register.
 22. Theapparatus of claim 20, wherein said second detecting means are HammingError detection means and said means for correcting the indicated biterror are Hamming Error correction means.
 23. The apparatus of claim 21wherein said shift register is an integrated semiconductor circuit. 24.The apparatus of claim 20 wherein at least one of said means forproviding an error output signal also halts the apparatus upon providingsaid error signal.
 25. Apparatus for detecting whether a track ofcycling sequential binary data bits is in an inalterable conditioncomprising means for complementing one of said bits in said track andfor inserting said complemented bit into said track as a check bit,means for detecting a change in the binary state in said cycling datatrack, means for cycling said track so that said check bit and itscorresponding original bit pass said detecting means, and meansresponsive to said detecting means for indicating that the track is inan inalterable condition in the absence of said detected change.
 26. Theapparatus of claim 25, wherein the entire data track is cycled past saiddetecting means, thereby insuring that the check bit and the originalbit will be cycled past said detecting means.
 27. The apparatus of claim25 wherein said detecting and indicating means comprise a bistablecircuit to which said check bit and said original bit are sequentiallyapplied, the output state of said bistable circuit indicating whetherthere has been a change in binary state between said two applied bits.28. The apparatus of claim 25 wherein said original bit passes saiddetection means immediately preceding said check bit.
 29. Apparatus fordetecting whether any of a plurality of tracks of cycling sequentialbinary data bits are in an inalterable condition comprising means forcomplementing one of saiD bits in each of said plurality of tracks andfor inserting each of said complemented bits respectively into saidplurality of tracks as check bits, means for detecting a change in thebinary state in each of said cycling data tracks, means for cycling saidtracks so that each of said check bits and their original bits pass saiddetecting means, and means responsive to each of said detecting meansfor indicating that the track corresponding to the detecting means is inan inalterable condition in the absence of a detected change.
 30. Theapparatus of claim 29 wherein each of said original bits passes itsrespective detection means immediately preceding its respective checkbit in each of said tracks.
 31. A method for detecting errors inparallel binary data made of a plurality of binary bits, each of saidbits being respectively produced by one of a plurality of data trackscomprising detecting which tracks are in an inalterable condition; by asingle error Hamming Code Detection method, detecting the presence of abit error condition in said binary data and indicating the proper bitposition in said data pattern of an error only when a single error ispresent in said pattern, and determining if said indicated random erroris coincident with a track determined to be in an inalterable condition.32. The method of claim 31, further including the steps of counting theinalterable tracks, detecting the presence of a parity error in thebinary data pattern, correlating said detected parity error, bit error,coincident and inalterable track conditions with said inalterable trackcount, and selectively complementing bits produced by at least one ofsaid inalterable tracks when said correlated conditions and countcorrespond to a predetermined combination of said conditions and count.33. The method of claim 31, further including the steps of counting theinalterable tracks, detecting the presence of a parity error in thebinary data pattern, correlating said detected parity error, bit error,coincident error and inalterable track conditions with said inalterabletrack count, and selectively correcting said indicated Hamming errorwhen said correlated conditions and count correspond to a predeterminedcombination of said conditions and count.
 34. The method of claim 33,further including the step of selectively complementing bits produced byat least one of said inalterable tracks when said correlated conditionsand count correspond to a predetermined combination of said conditionsand count.
 35. The method of claim 34 wherein said selective correctionis made when said predetermined combination includes a count of two. 36.The method of claim 32 wherein said selective complementing is made whensaid predetermined combination includes a bit error condition, no parityerror, two inalterable tracks and a coincident condition, and only theinalterable track which is not coincident with said indicated randomerror bit position is complemented.
 37. A method for detecting andcorrecting errors in a parallel binary data pattern made of a pluralityof binary bits, each of said bits being respectively produced by one ofa plurality of data tracks comprising determining which tracks are in aninalterable condition; counting the number of tracks in said inalterablecondition; halting the apparatus when the count of inalterable tracks isat least three; detecting the presence of a parity error in the parallelbinary data pattern; by a single error Hamming Code Detection methoddetecting the presence of an error condition in said binary data andindicating one of the bits in said data pattern, said indicated bitbeing in error only when there is a single error in said binary datapattern, applying said binary data pattern to said first and seconddetecting means; upon the combination of the absence of a parity errorand the presence of an error Condition in the applied data pattern, thencomplementing the bits in said parallel data pattern produced by tracksin inalterable condition; reapplying said complemented data pattern tosaid first and second detecting means; signaling an error if saidreapplied complemented data pattern still results in the combination ofthe absence of a parity error and the presence of an error condition;passing the original or reapplied data pattern as a good pattern in theabsence of both said parity error and error condition; upon thecombination of the presence of a parity error in the original orreapplied data pattern and an inalterable track count of less than two,then correcting said indicated bit error and for passing the correcteddata pattern as a good pattern; determining if said indicated bit erroris produced by a stuck track, and upon the combination of the presenceof a parity error in the original or reapplied data pattern and aninalterable track count of two, then correcting said indicated bit errorand for passing the corrected data pattern if said indicated bit erroris produced in a stuck track, or providing an error output signal ifsaid indicated bit error is not produced by a stuck track.
 38. A methodfor detecting whether a track of cycling sequential binary data bits isin an inalterable condition comprising inserting into the track, atleast one check bit which is the binary complement of the next precedingbit, and detecting whether there is a change in the binary state in saidcycling data track during one cycle of the track.